Position Title: Physical Design Manager

Primary Job Responsibilities:

Specific responsibilities include but are not limited to the following:

· Manage/Lead a team of 6-12 physical design engineers to execute all tasks from netlist/constraint handoff to GDS.

· Build, lead and manage a highly skilled engineering team to deliver quality/predictable/tight schedule and cost effective chips. These chips include complex Embedded PowerPC SoC, Network Processors, Framers/Mappers, FEC, Storage and 10GE phys. These products are in 130nm, 90nm, 65/55nm, and 45nm CMOS; chip sizes ranging from 3mm to 16mm per side with clock rates from 125MHz to 2.5Ghz.

· Define project plans, track project progress, provide technical direction and/or consultant to team members, interface with front-end/IP/LIB/Packaging team, and define/negotiate/resolve handoff criteria and sign-off criteria.

· Key driver/contributor to floorplan, hierarchical partitioning, complex clock scheme, clock tree synthesis, soft/hard IP integration and qualification, IO die to package map, PR, DRC/LVS, ECO, Timing/EM/Power/SI closure.

· Facilitate and work with cross functional group on IO signal integrity, ESD, Latchup, PDK kit, library preparation and tool qualification/evaluation.

· Track and resolve technical, execution, and resource issues.

· Work with internal team as well as cross functional team to develop and improve and design methodologies and project flows.

· Perform day-to-day reviewing, checking and managing the team.

· Responsible for maintaining and improving existing COT flow scripting and documentation.

· Responsible for researching other tool vendors, develop evaluation plan and carry out tool evaluation on both signoff and implementation flow.

Our team works designs from netlist to tape out using CAD tools such as Magma, StarRCXT, PrimeTimeSI, and Calibre. Scripting is Tcl and Perl. Other tools may be inserted in the flow as needed. Throughout the process, a high value is placed on design quality, repeatability of successful techniques, and depth of implementation checking.

Education Requirement or Equivalent:

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Physics or equivalent work experience is required.

Experience Requirement:

· An expert with hands-on experience as well as solid knowledge of physical design methodologies, tools and best practices.

· 10+ years BS/8+ years MS/6+ PhD years of hand-on physical design/implementation experience; or a combination of physical implementation, synthesis, chip integration, STA/DFT engineer.

· 6+ years of physical design experience with 4+ years using Magma physical design tools and Synopsys timing signoff tool.

· 3+ years management experience

· Have completed physical design in multiple complex projects from “Kick-Off” to tape-out and to production quality silicon. The candidate must have completed layouts on 3 or more chips that have been built in silicon and that work; must have resolved significant, non-routine design issues or problems; and must have contributed methodology solutions and scripting to design flows used by others.

· Experienced manager with proven ability to lead diverse and multi-location teams.

· Proven ability to deliver high quality results under pressure.

· Excellent communications skills to articulate and communicate project plans and requirements both to internal groups and to customers.

· Ability to collaborate with management and cross organizations to secure necessary buy-in and support.

· Passionate, driven and caring individual.

Special Skills or Knowledge Required:

· Required skills are in-depth understanding of the principles of CMOS design and digital logic circuitry, Synopsys constraint and proficiency at programming in Tcl, Perl, or C in the UNIX/Linux environment.

· Demonstrated ability to perform and complete projects as a group lead and individual contributor at the block or chip level using Magma physical implementation tools.

· It is required to have expert level skill using 3 or more, and some knowledge of how to configure 1 or more of the following tools: Magma/Astro/SoC Encounter, ChipBench, Physical Compiler/ Design Compiler, PrimeTimeSI,/EinsTimer, StarRCXT/Assura, Calibre/Hercules/Diva, or similar tools.