RFIC Manager: Terran Systems

Manager of RFIC Design:
As a RFIC Design Engineer you will perform transistor level design, partial layout and detail layout supervision, simulation, parasitic extraction, and worst-case analysis of variety of RF front-end circuit blocks such as LNA, and Mixer. This includes schematic capture, design documentation and layout review using Cadence tools. You would be leading directions for the junior design engineers. You must be disciplined and able to follow established design practices.
As a key member of the RFIC team, you are required to have a BS or MS, in Electrical Engineering, or equivalent. A minimum of 5 years of RFIC related industry experience in the following areas:
Experienced in full-custom CMOS, or BiCMOS circuit design, transistor level design of LNA, Mixer.
Bench testing and troubleshooting and working with spectrum and network analyzer,
On-Wafer characterization of RF circuits
Knowledge of passive elements used in RF circuits such as inductor and varactors
Knowledge of parasitic extraction of layout, package and PCB and its circuit modeling
Isolation schemes and their impact on RF circuits
EM coupling and tools specifically when it is related to on-chip inductors
Proficient with Cadence and Mentor graphics tools.

Please send a WORD VERSION of your resume to the following address:

ericw@terransys.com

Feel free to contact me directly at

408-727-9000

We look forward to hearing from you!

If you do not feel this position is a perfect match for please contact us in regards to out other positions. We have numerous needs in this area and welcome the opportunity to discuss your background.

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