Senior DSP ASIC Design Engineer: SiRF Technology, Inc

SiRF Technology develops and markets highly complex SOC products for Location and Wireless Communication applications that consist of high performance embedded processors, specialized DSP communication/location engines, embedded memories as well as external memory interfaces, and various I/O interfaces such as USB, UART, GPIO, etc.

We are seeking energetic hands-on Senior DSP ASIC Design Engineer for our DSP Design Team in Phoenix, AZ.

· Custom DSP processor design including OFDM, Linear Digital Filter Design and Matched Filter Design.
· GNSS applications involving embedded processor, SRAM, ROM, and DSP engine.
· Developing ASIC chips for low power and integration with other communication technologies.
· Developing derivative and cost reduced products through design and technology upgrades.

· MSEE degree preferably in Electronics and Communication field with emphasis on Digital Signal Processing and Communication Systems Architecture.

· Working knowledge of DSP design, verification and validation as applied to digital radio design. Candidates with GPS/Spread Spectrum Communication and Digital Filter Design, QAM, FEC, and FFT background will be preferred.
· 5+ years relevant experience and has taken 3 or more designs from specification to silicon.
· Must have good hands-on experience with RTL coding, simulation and synthesis. Must have been closely involved with P & R, timing closure, DFT, and ATE test vector generation.
· Background in SOC design involving embedded processors, standard bus architectures, I/O protocols, and memory design. Preference will be given to candidates with experience in low power design techniques.
· Experience with bench testing, debugging and silicon validation.

· Experience with FPGA design and prototyping is a plus.