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ASIC/SoC Design Engineers: Verification and Synthesis: TSL Associates

Company NameTSL Associates
Job CategoryEngineering/Architecture
LocationAustin, TX • Boston, MA
Position TypeFull-Time, Employee
Salary$80,000 to $110,000 per year
Experience2-5 Years Experience
Desired Education LevelBachelor of Science
Date PostedOctober 10, 2007 (Reposted Jul 1)
Apply Now: A Better Job Search Experience. Learn Why
Perform ASIC/SoC design verification for Digital Satellite , Imaging and Video IC applications!

Advanced development design centers are expanding! Join a top shelf team in the development of next generation IC's for wireless video, DTV, and digital satellite radio.
ASIC/ SoC Design Verification Engineers:

Must have a minimum of 2 to 10 years of experience. There are several levels of positions.
Strong Verilog skills needed! Must have solid experience with higher level tools such as System Verilog, Specman or Vera .
Knowledge of VMM, RVM, assertion:SVA, PSL , ARM or AMBA
ASIC/SoC Synthesis Engineers;
Must have a minimum of 2 to 10 years of experience. There are several levels of positions.
Must have experience in Synopsys, synthesis, primetime, and a solid understanding of backend applications.
Must have experience taking projects from RTL through all post RTL development such as synthesis, using Synopsys, scan insertion, equivalency checking, netlists, STA, etc.
Experience in 65nm , 90nm or 130nm technology.
Responsibilities:

- Module test plan and testbench development

- Synthesis and timing analysis

- Opportunity expand breadth of responsibilities depending on demonstrated motivation and skills

- Knowledge of RTL design, Verilog/VHDL

- Knowledge of Cadence NCsim, Synopsys DC

- Experience with Synopsys DC, PC, PT at both module and chip level

- Knowledge of programming and scripting languages such as C, C++, shell, perl, tcl

For confidential inquiries or to arrange an interview, please contact Todd Lyon at 716-751-6345 or tlyon@jobjungle.net

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