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SoC Timing Analysis Engineer;: AMCC-Applied Micro Circuits Corp.
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STA, Primetime and PTSI, Timing constraints, Perl, Tcl, DDR2/3
When people think of technology innovation, they think of AMCC. Our company leads the charge to create the essential building blocks that allow people to share and store information worldwide; we're moving fast and thinking fast – all the time. AMCC provides the foundation for major networking and telecommunications companies like Cisco Systems, Nortel Networks, Alcatel and Lucent Technologies. We work with well-known OEMs like SUN, Hitachi and HP to deliver leading HBA solutions for storage networks. Additionally, we target exciting, high-growth markets like Serial ATA (SATA) RAID. If you're interested in making an impact by driving the wave of innovation in the world of networking, see below. Chip Timing Analysis EngineerEngineering, Austin, TXRegular, Full-time position;Primary Job Responsibilities: In this Principal level position, you would be responsible for generating chip level constraints, exceptions, and achieving timing closure for a complex SOC with many clock domains and high speed IO. You will have to work with different engineering teams/functions so team work, communication, and strong initiative will be required.
Should be knowledgeable about floorplanning, routing, clock tree and DSM effects. Experience with DDR2/3, and knowledge of Perl and Tcl preferred. To be considered for an open position at AMCC, please send your resume to jobs@amcc.com . Please include the job title in the subject line (a plus).      |
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