MTS HW (Logic Design Engineer): Foundry Networks
- This is a senior design engineering position.
- Work closely with other team members and/or other members of the Hardware Group {board & system development}, as well as various members of the software group.
- The job concept is to aid and/or lead in the development and verification of Foundry developed ASICs or FPGAs which are deployed in our switching and routing products.
- The scope of contribution includes hardware engineering, software engineering, and may extend to both architecture development and manufacturing release.
- Frequent mousing and keyboarding.
- Frequent phone usage.
Day-to-Day Responsibilities:
- Independent development of test-case definition and implementation, test-harness definition and implementation, and ASIC/FPGA logic design.
- Candidate will assist other engineers in the development, test deployment, and bug discovery/closure process for ASIC/FPGA verification and/or model development.
- Duties include most of the following: the RTL design, debug of various logic blocks {including timing closure}, the writing, review, and release of test-case/test-harness documentation, the RTL coding of test-cases and/or a test-harnessthe design and maintenance of regression level test-suites, the evaluation of new CAE tools, netlist generation, netlist timing analysis and closure, test-vector generation, gate-level verification, Boolean equivalence verification, margin analysis, signal integrity.
- Technical contributions on new architectural definition/proposals, new technology evaluation, and team-leadership skills are expected
- A minimum of 10+ years general engineering practice, with proven track record of significant ASIC and/or FPGA design and verification experience over the last 5+ years.
- Proficient with UNIX, Linux environment C-shell or Bourne shell, as well as shell-script programming.
- Demonstrated proficiency and relevant experience with the Verilog programming language and Synopsys/Synplicity synthesis tool is required.
- Demonstrated core-competency in solid logic design practice is required.
- Experience with C-shell programming highly desirable, along with some experience in one or more of the following: PERL, SED, AWK, TCL/TK, Makefiles.
- A minimum of 3 years experience with LAN/MAN/WAN networking technology is required.
- A minimum of 6+ years practical hands-on experience with most ALL of the following CAE tools: Verilog or VCS, Synopsys, Primetime, Formality, Code coverage tool, Debussy, SignalScan-TX, Synplicity,
|
